Semiconductor chips may be divided into a number of different discrete categories, analog, digital, and memory devices, depending on the characterization. To accommodate the increasingly stringent requirements of today's semiconductor industry, analog, digital and memory devices often require production monitoring and testing. Production monitoring is typically performed using “in-line” inspection equipment, and production testing is performed using “end-of-line” test equipment. In-line inspection equipment often inspects entire semiconductor wafers, each of which may have formed thereon hundreds of chips. End-of-line test equipment performs “electrical testing” on semiconductor wafers in which the pads of chips are contacted and the chips “exercised.”
Apart from production testing is failure analysis. Failure analysis attempts to identify the cause of failures of chips of a particular chip design after those failures have been detected during production (or prototype) testing. Failure analysis may typically acquire more detailed failure information than that provided using the production (or prototype) testing.
Digital and memory devices, because of their structure as regular arrays of memory cells, readily lend themselves to end-of-line production testing. The memory cells of the digital and memory devices may be tested by performing a series of read and write operations to the memory cells. Errors in read/write testing may be pinpointed as likely physical defects at readily identifiable locations on the chip. Alternatively, the digital and memory devices' designs may contain built-in self-test (BIST) capabilities. In either case, functional test results can be “bitmapped” to failure locations on the memory chip. In memory bitmapping, electrical failures are localized within a relatively small physical “trace” on the die.
Unfortunately, analog devices have little or no memory cells to accurately discern defect origins like their digital and memory device counterparts. Current and historic work to capture defect loss for analog devices is relegated to using test chips. The information discerned from the test chips, however, must then be attributed (e.g., extrapolated) to represent the actual product wafers. Thus, the information discerned is not one to one, because what you detect in a test chip may or may not be present in a production chip. Moreover, running test chips is expensive and takes away from resources that might be used to make production chips.
Accordingly, what is needed in the art is a technique for an end-of-line production testing methodology for analog devices with the ability to map & overlay physical defect information.